IEEE ADIT Student Branch - Events

Seminar on “Overview of VLSI and advanced challenges in VLSI domain”

By April 1, 2019 April 23rd, 2019 No Comments

Coordinator: Dr. Rutvij C. Joshi (EC)

Convener: Dr. Hetal N. Patel, Head, ECE Department, A.D.I.T

 

One day seminar was arranged on “Overview of VLSI and Advance Challenges in VLSI Domain” by the experts from e-Infochips, Ahmedabad on 12th July 2018 at A. D. Patel Institute of Technology, New Vallabh Vidyanagar. The seminar mainly focused on introduction and overview of VLSI Technology and advance challenges in design and fabrication of chip. Dr. Hetal N. Patel, convener of the program and Dr. Rutvij C. Joshi, Coordinator of the program have Well-come the experts. Ms. Dhruv Rutvi (Student of A.D.I.T) has introduced both speakers to the audience. Seminar was started with the speech of Mr. Pavan Vora , (ASIC Engineer, e-Infochips, Ahmedabad). He has given very interesting talk on evolution of transistor technology and MOS Technology. He has also introduced New FinFET technology for IC fabrication. Second session was conducted by Mr. Chairag Maniya, (Technical Lead, e-Infochips, Ahmedabad). He has explained design and fabrication process along with challenges

associated with these processes. He has also introduced carrier options/ job prospects in VLSI domain. Both sessions are highly informative and fruitful. Both speakers have addressed all queries/doubts of faculties and students. At the end of the session, the speakers were offered mementos from Prof. Hiren Soni and Dhruv Rutvi (Student). The session was concluded with vote of thanks by Dr. R. C. Joshi, coordinator of the event.

No of Participants: 46

Event Type: Technical

Event Level: Branch

Date: July 12, 2018

Duration: Half Day

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